To get a first clue about the Load Line, I will use an example with a Common Emitter amplifier with voltage divider biasing for the base. More details are yet to come for each connection type. Here is the circuit:

For an instance, let's forget about the input portion of the circuit (the voltage divider) and let's work only with the output portion. According to Kirchhoffs' law we have:

Let's now calculate the first point of the load line. This point (like any other point in a x-y Cartesian system) has 2 terms: an x and a y term. We need to find a V_CE and a I_C pair of values which corresponds to the x and y terms respectively. We can make this calculation much easier with a simple and common trick: We will calculate a V_CE value for I_C=0. This way, the first pair will be on the V_CE axis. Let's solve the previous equation for V_CE:

First thing that we notice is that I_C x R_C is zero, since I_C is zero. V_E is zero as well, because I_E is -almost- equal to I_C, and V_E is equal to I_E x R_E. The equation can be re-written as follows:

Now for the second pair. Similarly, we will calculate a I_C value for V_CE = 0. So, the second point will be on the I_C axis. Let's solve for I_C:

And since we defined that V_CE = 0:

So, now we have the 2 points that we need to draw the load line. The points are:

The green dots indicate the 2 points of the load line, and the red line is the DC load line itself.

We will continue the previous example and we will calculate the Q point. There is something that you need to make clear: The Q point is a point on the Load Line. The Load Line is calculated (as we saw before) by finding two points in the cut-off and saturation area. The Q point is usually placed within the linear area. The Q point is determined by the DC biasing of the transistor. The fact that the circuit uses VDB (Voltage divider Bias), allows us to neglect the base current in our calculations. So, the base voltage is:

We can now calculate the emitter voltage as follows:

And the emitter current is:

And since the collector current is almost equal to the emitter current, we can calculate the voltage drop across R_C as follows:

Finally, the Collector-Emitter voltage is calculated as follows:

Now we have everything we need to set the Q point:

Let's analyze for one moment what we've done so far. First, we found two points to draw the load line. The first point was found on the V_CE axis by zeroing the I_C current, and the other point was found on the I_C axis by zeroing the V_CE voltage. Both points were calculated with the same equation:

For the first point we solved this equation for V_CE, and for the second we solved it for I_C. Then, we calculated the Q point. For the Q point, we need another pair of I_C-V_CE values. These values are calculated from the DC transistor bias. If the DC bias is not in the cut-off or in the saturation area, then it must be somewhere on the DC load line that we draw before. That is true since both the load line points and the quiescence point are calculated with the exact same equation. The only difference is that for the load line, we choose (for our own ease and only) to find points on the two axis, whilst for the quiescence point we solve the equation for the DC values defined by the biasing resistors.

Since the quiescence point is only one, and since the I_C and V_CE values of the quiescence point are critical, we usually use the pointer "q". So, for the quiescence V_CE voltage we use the symbol V_CEq, and for the quiescence I_C current we use the symbol I_Cq.

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